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The following recursive VHDL function provides the needed bit count for a given integer number. function len(x: integer) return integer is begin if (x<=1) then return 1;  else return 1+len(x/2); end if; end len;

This solution solves the issue on, how to detect either one or more bits are active in a bit array. The technique is quite easy, just isolate one of the bits. This can be done by the same technique as known from the arbiter implementation. Calculate the two’s complement of the bit array signal and Continue reading →

Here a very cute method to implement an FPGA round robin arbiter, inspired by [1]. Assumption Incoming signals “req”/”ack”, outgoing signal “grant”. Needed Behaviour req = “0001000″ => grant = “0001000″ -ACK- grant = “0001000″ req = “0011000″ => grant = “0010000″ -ACK- grant = “0001000″ -ACK- grant = “0010000″ … Technique To create a Continue reading →

Today I want to use the attached DDR2 Ram on the ml50x (XUPV5) board. Xilinx provides a Memory Interface Generation (MIG) IP core which could be used to generate a design which drives all ddr2 lines and provides an interface for user logic. It is extremely sadly that xilinx doesn’t provide directly the needed ucf-files Continue reading →

Great, the FPGA board has a piezo speaker soldered. This is the next funny component to drive. The device is connected with one wire, where the FPGA has to send a pulsing signal to it. Typical this signal will be generated by a frequency generation module. The sending frequency of the implemented module can be Continue reading →

Today it was time to write some VHDL code for the new board. The result are some lines to drive the LCD (ks0066u chipset 4-Bit interface). It is quite easy to talk with such devices, they have only a 4 bit data bus, 1 RS (Register Select), 1 R/W (Read/Write) and 1 E (Read/Write Enable) Continue reading →