un.codiert.org

Here a very cute method to implement an FPGA round robin arbiter, inspired by [1]. Assumption Incoming signals “req”/”ack”, outgoing signal “grant”. Needed Behaviour req = “0001000″ => grant = “0001000″ -ACK- grant = “0001000″ req = “0011000″ => grant = “0010000″ -ACK- grant = “0001000″ -ACK- grant = “0010000″ … Technique To create a Continue reading →

During the vacation time a lot of code changes were made. Now it is time to write a little bit about the changes. The first thing was to write a Cypress USB to wishbone interface which gave the possibility to connect wishbone compliant modules to USB. As testcase the wishbone lcd driver should help to Continue reading →

Today I want to use the attached DDR2 Ram on the ml50x (XUPV5) board. Xilinx provides a Memory Interface Generation (MIG) IP core which could be used to generate a design which drives all ddr2 lines and provides an interface for user logic. It is extremely sadly that xilinx doesn’t provide directly the needed ucf-files Continue reading →

Ok, now the second part of this cypress story. The source which is provided by cypress contains some demo projects, for my test design which should put the board into a peripheral mode, the demo “de2″ is a good starting point. After some browsing through the code I saw that this demo puts SIE1 (Serial Continue reading →

Time to play with the next part of the ML505 board. The soldered USB chip is provided by Cypress and can be configured as a host and peripheral device. It contains a 16-Bit Risc Core, two serial interface engines (4 USB Ports) and a lot of other useful things (UART, SPI, IDE interface). To provide Continue reading →

Great, the FPGA board has a piezo speaker soldered. This is the next funny component to drive. The device is connected with one wire, where the FPGA has to send a pulsing signal to it. Typical this signal will be generated by a frequency generation module. The sending frequency of the implemented module can be Continue reading →

Today it was time to write some VHDL code for the new board. The result are some lines to drive the LCD (ks0066u chipset 4-Bit interface). It is quite easy to talk with such devices, they have only a 4 bit data bus, 1 RS (Register Select), 1 R/W (Read/Write) and 1 E (Read/Write Enable) Continue reading →

Today the a new development board received. It has an Virtex5 FPGA soldered and a lot of I/O connections. It is sold by Digilent Inc. as “Virtex-5 OpenSPARC Evaluation Kit”. Digilent has soldered a Virtex5 110T on the board instead of a Virtex5 50T as Xilinx on the ML505. All other components on the board Continue reading →