Publications

  • B. Krill, A. Amira and A. Ahmad, „FPGA optimised 3-D cyclic convolution using dynamic partial reconfiguration“, Information Science, Signal Processing and their Applications (ISSPA), 2012 11th International Conference, Pages 973-977, 2-5 July 2012, Montreal.
  • B. Krill, A. Amira and H. Rabah, „Generic virtual filesystems for reconfigurable devices“, Circuits and Systems (ISCAS), 2012 IEEE International Symposium, Pages 1815-1818, 20-23 May 2012, Seoul.
  • A. Ahmad, A. Amira, P. Nicholl and B. Krill, „FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration“, Springer Journal of Real-Time Image Processing, Issue 8, Volume 56, pp 1-14, Sep 2011
  • B. Krill, A. Amira, „Efficient Reconfigurable Architectures of Generic Cyclic Convolution“, 15th IEEE Symposium on Consumer Electronics (ISCE), 14.-17. June 2011, Singapure.
  • A. Ahmad, P. Nicholl, A. Amira, B. Krill, „Dynamic Partial Reconfiguration of 2-D Haar Wavelet Transform (HWT) for Face
    Recognition Systems‘”, 15th IEEE Symposium on Consumer Electronics (ISCE), 14.-17. June 2011, Singapure.
  • Mhd Saeed Sharif, M. Abbod, B. Krill, A. Amira, H. Zaidi, „Automatic Pet Volume Analysis And Classification Based on ANN and BIC’”, 15th IEEE Symposium on Consumer Electronics (ISCE), 14.-17. June 2011, Singapure.
  • B. Krill, A. Ahmad, A. Amira and H. Rabah, „An New FPGA-Based Dynamic Partial Reconfiguration Design Flow And Environment For Image Processing Applications“, 2nd European Workshop on Visual Information Processing (EUVIP), 5.-7. July 2010, Paris.
  • H.Baier, M.Drochner, N.Eicker, G.Goldrian, U.Fischer, Z.Fodor, D.Hierl, S.Heybrock, B.Krill, T.Lippert, T.Maurer, N.Meyer, A.Nobile, I.Ouda, H.Penner, D.Pleiter, A.Schäfer, H.Schick, F.Schifano, H.Simma, S.Solbrig, T.Streuer, K.-H.Sulanke, R.Tripiccione, T.Wettig, F.Winter, “Qpace: Power-efficient parallel architecture based on IBM PowerXCell 8i”, EnA-HPC 16.-17. September 2010, Hamburg.
  • B. Krill, A. Ahmad, A. Amira and H. Rabah, „An Efficient FPGA-based Dynamic Partial Reconfiguration Framework for Image and Signal Processing IP Cores “, Elsevier Journal of Signal Processing: Image Communication, May 2010.
  • A. Ahmad, B. Krill, A. Amira and H. Rabah, „Efficient Architectures for 3D HWT using Dynamic Partial Reconfiguration“, Elsevier Journal of System Architecture – Special Issue on Hardware/Software Co-Design, February 2010.
  • S. Rinke, B. Krill, H. Böttiger, „QPACE: Energy-Efficient High Performance Computing“, 23 PARS – Workshop on Parallel Systems and Algorithms (PARS 2010), 22.-25. February 2010, Hannover.
  • A. Ahmad, B. Krill, A. Amira and H. Rabah, „3D Haar Wavelet Transform with Dynamic Partial Reconfiguration for 3D Medical Image Compression“, The IEEE Biomedical Circuits and Systems Conferences (BIOCAS), November, 26.-28. 2009, Beijing, China.
  • B. Krill and A. Amira, „FPGA Implementation of Image and Signal Processing IP cores Using Dynamic Partial Reconfiguration”, The 2nd SED Research Student Conference (ReSCon 2009), Brunel University, 22.– 24. June 2009, West London.
  • B. Krill and A. Amira, „FPGA Implementation of Image and Signal Processing IP cores Using Dynamic Partial Reconfiguration”, Graduate School Research Student Poster Conference, Brunel University, 6-7 May 2009, West London.
  • B. Krill and A. Amira, „A Reconfigurable System for IP Cores Generation based Image and Signal Processing Applications”, The 1th SED Research Student Conference (ReSCon 2008), Brunel University, 25.-26. July 2008, West London.
  • H.Baier, M.Drochner, N.Eicker, G.Goldrian, U.Fischer, Z.Fodor, D.Hierl, S.Heybrock, B.Krill, T.Lippert, T.Maurer, N.Meyer, A.Nobile, I.Ouda, H.Penner, D.Pleiter, A.Schäfer, H.Schick, F.Schifano, H.Simma, S.Solbrig, T.Streuer, K.-H.Sulanke, R.Tripiccione, T.Wettig, F.Winter, “Qpace: QCD parallel computing on the CELL”, Computing in Science and Engineering 2008.

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