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When the XUPV5 board arrived (in 2008) it already was configured to boot OpenSolaris on the OpenSPARC T1 processor. I just did a short boot and looked at the serial prompt. This was the whole experience I made with the default set-up. Since the board was needed for other projects, I deleted the files from Continue reading →

Again the issue with the Xilinx JTAG cable under Linux. This post is just a reminder… After putting the cable into the USB port, nothing happens. ‘lsusb’ shows the device but the led on the JTAG box doesn’t light up, which means the firmware isn’t loaded. The firmware is provided by Xilinx and it can Continue reading →

The following recursive VHDL function provides the needed bit count for a given integer number. function len(x: integer) return integer is begin if (x<=1) then return 1;  else return 1+len(x/2); end if; end len;

This solution solves the issue on, how to detect either one or more bits are active in a bit array. The technique is quite easy, just isolate one of the bits. This can be done by the same technique as known from the arbiter implementation. Calculate the two’s complement of the bit array signal and Continue reading →

Here a very cute method to implement an FPGA round robin arbiter, inspired by [1]. Assumption Incoming signals “req”/”ack”, outgoing signal “grant”. Needed Behaviour req = “0001000″ => grant = “0001000″ -ACK- grant = “0001000″ req = “0011000″ => grant = “0010000″ -ACK- grant = “0001000″ -ACK- grant = “0010000″ … Technique To create a Continue reading →

During the vacation time a lot of code changes were made. Now it is time to write a little bit about the changes. The first thing was to write a Cypress USB to wishbone interface which gave the possibility to connect wishbone compliant modules to USB. As testcase the wishbone lcd driver should help to Continue reading →

Today I want to use the attached DDR2 Ram on the ml50x (XUPV5) board. Xilinx provides a Memory Interface Generation (MIG) IP core which could be used to generate a design which drives all ddr2 lines and provides an interface for user logic. It is extremely sadly that xilinx doesn’t provide directly the needed ucf-files Continue reading →

Ok, now the second part of this cypress story. The source which is provided by cypress contains some demo projects, for my test design which should put the board into a peripheral mode, the demo “de2″ is a good starting point. After some browsing through the code I saw that this demo puts SIE1 (Serial Continue reading →

Time to play with the next part of the ML505 board. The soldered USB chip is provided by Cypress and can be configured as a host and peripheral device. It contains a 16-Bit Risc Core, two serial interface engines (4 USB Ports) and a lot of other useful things (UART, SPI, IDE interface). To provide Continue reading →

Great, the FPGA board has a piezo speaker soldered. This is the next funny component to drive. The device is connected with one wire, where the FPGA has to send a pulsing signal to it. Typical this signal will be generated by a frequency generation module. The sending frequency of the implemented module can be Continue reading →