un.codiert.org

Today I want to use the attached DDR2 Ram on the ml50x (XUPV5) board. Xilinx provides a Memory Interface Generation (MIG) IP core which could be used to generate a design which drives all ddr2 lines and provides an interface for user logic. It is extremely sadly that xilinx doesn’t provide directly the needed ucf-files for all boards they sale. Everybody who wants to use the MIG has to create the ucf by himself or looking for reference designs where this file is included. Fortunately the ucf exists for the xupv5 board. So I only have to care about the user logic which writes or reads from the memory. The user interface is well documented in the user guide (ug086) and could be driven with some lines of code. Keep reading, now it is time to combine some already written logic with the mig.

This entry was posted on Sunday, November 23rd, 2008 at 20:45 and is filed under FPGA.You can follow any responses to this entry through the RSS 2.0 feed. Responses are currently closed, but you can trackback from your own site.