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Today I want to use the attached DDR2 Ram on the ml50x (XUPV5) board. Xilinx provides a Memory Interface Generation (MIG) IP core which could be used to generate a design which drives all ddr2 lines and provides an interface for user logic. It is extremely sadly that xilinx doesn’t provide directly the needed ucf-files Continue reading →

Since Fedora 9, the init process is managed by upstart. To get a serial console with a login prompt the old method doesn’t work anymore. The old method is to add the following line into /etc/inittab: s0:3:respawn:/sbin/agetty -L 115200 ttyS0 vt100 This spawns a agetty for the ttyS0 in runlevel 3. The new method is Continue reading →